1. Field of the Invention
The present invention relates to SRAMs, and more specifically to means for setting such memories to a power consumption stand-by mode when these memories do not have to be used, either in the write or in the read mode.
2. Discussion of the Related Art
FIG. 1 schematically shows a static memory point having a conventional structure. Memory point 1 includes inverters 2 and 4 connected in anti-parallel. The respective inputs of inverters 2 and 4 are connected to respective bit lines BL1, BL2 via switches 8, respectively controlled by row selection signals WL1 and WL2. Each inverter is supplied between a high voltage V.sub.DD and a low voltage GND, currently, the ground. It should be noted that from the point of view of their supply, inverters 2 and 4 are in parallel.
To write an item of data in memory point 1, a voltage V.sub.DD is applied on one of bit lines BL1, BL2 and a voltage GND is applied on the other. Then, switches 8 are closed to set the state of the inputs and outputs of inverters 2 and 4. The switches are then opened and the state of the signals across the inverters is maintained.
To read an item of data from memory point 1, each of bit lines BL1, BL2 is precharged to a median voltage included between voltages V.sub.DD and GND, then switches 8 are closed so that the voltages present at the output of inverters 2 and 4 increase or decrease the bit line voltage. A read amplifier (not shown) connected to the bit lines amplifies these voltage variations and provides a binary information in relation with the data stored in the memory point.
FIG. 2 shows an embodiment of memory point 1 of FIG. 1. Inverter 2 includes a P-channel MOS transistor PMOS2, in series with an N-channel MOS transistor NMOS2. The source of transistor PMOS2 is connected to voltage V.sub.DD and the source of transistor NMOS2 is connected to voltage GND. The drains of transistors PMOS2 and NMOS2 are also interconnected at a node 02.
Similarly, inverter 4 includes transistors PMOS4 and NMOS4 connected like transistors PMOS2 and NMOS2, the gates of transistors PMOS4 and NMOS4 being connected to terminal O2 and the common drain of transistors PMOS4 and NMOS4 being connected to terminal O4.
In a first state, corresponding to the storage of a first item of data, transistors PMOS2 and NMOS4 are on while transistors NMOS2 and PMOS4 are off, and in a second state corresponding to the storage of the complementary data, transistors PMOS2 and NMOS4 are off while transistors NMOS2 and PMOS4 are on. Tile state in which transistors PMOS2 and NMOS4 are on and transistors NMOS2 and PMOS4 are off has been shown as an example. Then, transistors PMOS2 and NMOS4 substantially correspond to a short-circuit schematized by dotted lines and transistors NMOS2 and PMOS4 correspond to resistors RDS2 and RDS4.
The equivalent diagram of the memory point is then such as shown in FIG. 3. Generally, it should be noted that any memory point of the type of that in FIG. 2, whatever its programming state, has as an equivalent diagram to what is shown in FIG. 3, that is, two parallel resistors of substantially equal value R.
FIG. 4A shows a column formed of n memory points of the type of that in FIG. 1 supplied between voltage V.sub.DD and ground GND.
FIG. 4B shows an equivalent electric diagram in steady state of the column of FIG. 4A. 2n resistors of value R are connected in parallel between the supply terminals. The equivalent resistor has a value R/2n.
Each column will conduct a leakage current equal to (2n/R)V.sub.DD. The leakage current increases with the value of V.sub.DD and with the number of cells. It decreases when the values of the resistors in the off state of each transistor increase. Given the proportionality between the leakage current and the number of cells in a column, it should be clear that the larger the memory size, the more serious this leakage current and memory power consumption problem becomes. This problem is most serious in the case of portable devices, the memories of which are supplied by batteries.
For a memory of given size, it is obvious that to reduce the power consumption, the off-state resistance of each element has to be increased or the memory supply voltage has to be decreased. Studies made in both directions have come across serious difficulties.
To increase the off-state resistance of each transistor in a circuit raises difficult technological problems. Especially, in the case of a CMOS technology, even though increasing the resistance of the transistors of one conductivity type is relatively easy, it is difficult to simultaneously increase the resistance of the transistor of opposite type.
As concerns voltage V.sub.DD applied to a memory cell, it is imposed by the cell operation. It has however been devised to implement, for memories, as is already well known for logic circuits in general, a stand-by mode. In this stand-by mode, the reduced voltage would be applied during the inactive phases of the circuit, that is, in the case of a memory outside read and write phases. However, this solution has been discarded since, when the voltage across a memory point decreases below a given threshold, the memory point is likely to return to a basic state or to switch states in response to disturbances.